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TriMedia is a family of very long instruction word media processors from NXP Semiconductors (formerly Philips Semiconductors). TriMedia is a Harvard architecture CPU that features many DSP and SIMD operations to efficiently process audio and video data streams. For TriMedia processor optimal performance can be achieved by only programming in C/C++ as opposed to most other VLIW/DSP processors which require assembly language programming to achieve optimal performance. High-level programmability of TriMedia relies on the large uniform register file and the orthogonal instruction set, in which RISC-like operations can be scheduled independently of each other in the VLIW issue slots. Furthermore, TriMedia processors boast advanced caches supporting unaligned accesses without performance penalty, hardware and software data/instruction prefetch, allocate-on-write-miss, as well as collapsed load operations combining a traditional load with a 2-taps filter function. TriMedia development has been supported by various research studies on hardware cache coherency, multithreading and diverse accelerators to build scalable shared memory multiprocessor systems. ==Features== * 5 to 8 issue slots filled with up to 45 functional units * 128 32-bit general purpose registers * SIMD & DSP operations * 32-bit IEEE 754 floating point operations * 8/16/32/64 KB Instruction cache, 8/16/32/64/128 KB Data cache * separate memory and peripheral bus interfaces * up to 8 built-in timers * up to 64 built-in vectored interrupts * supported by an ANSI compliant C/C++ compiler toolchain 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「TriMedia (mediaprocessor)」の詳細全文を読む スポンサード リンク
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